(1) Field of the Invention
The present invention relates to a flash memory cell and method for operating the same, and more particularly, to a multi-bit flash memory cell having a theoretical minimum area of 8 F2 and method for operating the same.
(2) Description of the Related Art
A flash memory device is a type of non-volatile memory that allows multiple data writing, reading and erasing operations. The stored data of flash memory is retained even after power to the device is removed. With these advantages, flash memory has been broadly applied to personal computer and electronic equipment. One typical flash memory cell used in the flash memory is a tunnel oxide EPROM cell known as an ETOX-type cell (ETOX is a trademark of Intel Corp.).
FIG. 1 is a cross-sectional view of an ETOX-type cell 10 according to the prior art. The ETOX-type cell 10 includes a substrate 12 of one conductivity type such as P-type, a source region 14 and a drain region 16 of the opposite conductivity type such as N-type selectively provided in the substrate 12, a gate insulating film (a tunnel insulating film) 18 provided on the substrate surface, a floating gate 20 (a floating gate electrode) provided above the substrate 12 via the gate insulating film 18 between the source region 14 and the drain region 16, and a control gate (a control gate electrode) 24 provided above the floating gate 20 via an interlayer insulating film 22.
In such a flash memory cell, during writing (programming) operation a low voltage (for example, 0V) is given as the source voltage VS, a low voltage (for example, 0V) is applied to the substrate 12, a high voltage VPP (for example, 12V) is given as the control gate voltage VCG, and a high voltage is applied as the drain voltage VD. Consequently, a turn-on current flows between the drain region 16 and the source region 14, producing pairs of hot electrons and hot holes in the vicinity of the drain region 16. Those holes flow into the substrate 12 as a substrate current. In contrast, hot electrons are injected into the floating gate 20 to increase the threshold level with respect to the control gate 24, thereby completing the writing operation.
Data-erasing is carried out by applying the high voltage VPP and a low voltage (for example, 0V) to the source region 14 and the control gate 24, respectively, and setting the drain region 16 to a floating condition. At this state, a floating gate potential voltage VFG is set according to both the ratio of the capacity between the control gate 24 and the floating gate 20 to the capacity between the floating gate 20 and the source region 14, and the source voltage VS. Therefore, Fowler-Nordheim tunnel current flows through the thin tunnel insulating film 18 (approximately 10 nm) provided between the source region 14 and floating gate 20. Thus, electrons are reduced from the floating gate 20 to complete the erasing operation (the threshold level becomes the condition before writing).